`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/07/07 16:43:32
// Design Name: 
// Module Name: reg_IF
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module reg_IF(
    input wire clk,
    input wire rst_n,
    input wire [31:0] pc,
    input wire [31:0] inst_in,
    output reg [31:0] inst_out,
    output reg [31:0] pc_out,
    input wire id_data_hazard,
    input wire if_inst_hazard
    );

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)     pc_out <= 32'h0000_0000;
    else if(id_data_hazard||if_inst_hazard)  pc_out <= pc_out;
    else           pc_out <= pc;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)    inst_out <= 32'h0000_0000;
    else if(id_data_hazard||if_inst_hazard) inst_out <= inst_out;
    else          inst_out <= inst_in;
end

endmodule
